Specialties
Where we go deeper than most
Five areas where public knowledge is thin and we have shipped repeatedly. Each cuts across the three stages.
Tensilica DSP & TIE
Core configuration, memory integration, TIE-attached accelerators, XTOS and XOS firmware. Cadence partner. Two people with production TIE experience.
Baremetal ARM: CoreSight & SMMUv3
Trace, debug and address translation brought up with no kernel driver in the loop, on emulation and on silicon.
Co-Simulation Platforms
QEMU and host-speed processor models driving cycle-accurate RTL through AXI, AHB, APB and TIE transactors.
Spec-Driven RTL Delivery
Controlled specifications, change notes, decision registries and integration benches for RTL teams spread across companies.
Camera & Sensor Pipelines
MIPI, GMSL2, GigE Vision, HDMI and event cameras, from PHY to frame buffer to accelerator.