Case studies
Client names are withheld under NDA. Every study describes what we owned, the tools we used, and what shipped. One AR client has renewed with us every year since 2019, across every stage of two silicon generations.
Architecting a five-stage visual tracking accelerator for a multi-camera XR SoC
Hardware architect of record for a fixed-function accelerator that turns four concurrent camera streams into a real-time 6DOF tracking match set, coordinating the client's RTL designers across fifteen IP repositories.
Making Tensilica DSPs a platform: integration guidelines, core wrapping and accelerator attachment for a multi-DSP AR SoC
A platform-wide integration guideline every Tensilica core on the SoC follows, a repeatable core-wrapping procedure with foundry memory macros, and an accelerator attachment model built on TIE queues and shared data RAM.
From DSP feasibility to pre-silicon sign-off for a two-chiplet LiDAR ASIC
Six consecutive statements of work in fourteen months: algorithm-to-DSP feasibility, an emulation strategy study, software-driven pre-silicon verification of two chiplets, QEMU-to-RTL co-simulation, and DMA tooling the client later bought as source.
CoreSight verification on Veloce, with a clock-domain-crossing defect caught before RTL freeze
Baremetal tests across ARM-A and ARM-M cores proving every CoreSight component connected and operational for a mission-mode crash-dump facility, run on Siemens Veloce ahead of tape-out.
A production multi-client AXI-Stream DMA engine inside a dual-camera capture bridge
A parameterized native DMA engine with its own micro-architecture specification, shipped inside a multi-clock dual-camera capture bridge with full timing closure on a 7-series FPGA.
Three custom IP blocks for a low-power AR SoC: hardware logging, mailbox synchronization and event generation
Architectural specifications for three infrastructure IP blocks, RTL and verification for two of them, oversight of the third, and integration guidance to the chip team.
A visual-assist wearable for the blind and visually impaired, from research concept to Versal AI Edge prototype
Industry hardware partner on an NIH-funded assistive-vision program: headset and compute-pack architecture on a Versal AI Edge module, event and RGB camera integration, board and camera-interface design, and a SLAM front-end accelerator concept.
A Versal FPGA prototyping platform for a perception SoC: software architecture, Linux and real-time bring-up, MIPI display path and multicore DSP debug
System software architecture, embedded Linux and real-time runtime bring-up, a MIPI CSI-RX to DSI-TX loopback platform, and DSP debug over JTAG and CoreSight on a Versal MPSoC, closed with a signed completion report.
Custom smart camera, 2007. Virtex-4 FPGA, CMOS sensor module, Ethernet. Delivered to a retail video-analytics customer.
Twenty years of putting vision in hardware
The keypoint pipelines and camera bridges we build today descend from work that started before the firm did. A few of the roots:
2007 · FPGA smart camera
A custom camera board built around a Xilinx Virtex-4: sensor interface, on-board processing and Ethernet out, designed and delivered as a complete product for a retail video-analytics customer. Its face-detection pipeline was published at FPL 2007.
2016 · Visual region-of-interest detection
Saliency-driven ROI detection as the first stage of a visual object detection pipeline, on IBM POWER8 with the Coherent Accelerator Processor Interface. Demonstrated at OpenPOWER Summit and SuperComputing 2016.
2015 · FPGA-accelerated SURF features
Scale- and rotation-invariant feature extraction on HD imagery above 30 frames per second, for registration, tracking and augmented reality. The direct ancestor of today's keypoint pipelines.