Camera & Sensor Pipelines
Every vision accelerator starts with getting pixels in. We have built the receive path for most of the interfaces a camera can present, and the DMA and buffering behind it. We have been doing it since we built our first smart camera in 2007.
Interfaces
- MIPI CSI-2 and DSI on Versal, including lane-placement rules and FMC adaptor validation.
- GMSL2 and FPD-Link serializer paths for cameras placed far from the FPGA.
- GigE Vision receiver implemented in RTL through the Ethernet, IPv4, UDP and GigE camera protocol layers, with multi-channel DMA on Kintex UltraScale.
- HDMI receive datapath bring-up on Versal transceivers with external PHY boards.
- NTSC and PAL analog capture and display with color conversion and resampling.
- Event cameras integrated alongside frame sensors for low-latency, low-power front ends.
Behind the interface
- Multi-camera capture into off-chip memory with custom multi-clock arbitration.
- Parameterized multi-client DMA engines with their own micro-architecture specification.
- Row-cache buffers, patch collation and streaming keypoint pipelines feeding accelerators or AI Engine arrays.
- Camera selection, sensor bridge design, smart-camera PCB and schematics when the prototype needs its own hardware.