SiliconScapesArchitecture · RTL · Prototype
Specialties

Co-Simulation Platforms

Software should not wait for silicon, or even for RTL. Our co-simulation platform connects software execution domains to hardware simulation domains so both sides make progress from day one.

Host domainQEMU (ARM, Xtensa ISS)Host-speed processor modelC/C++ tests and firmwareTransactorsAXI · AHB · APB · TIE queuesSystemVerilog DPI / FLIsocket to remote hostsSimulation domainRTL: Xcelium, Questa, VCSEmulation: Palladium, VeloceFunctional subsystem models

QEMU to RTL

QEMU bridged to Xcelium, Questa and ModelSim over a foreign-language interface, with a network layer for remote hosts on Linux and Windows. Kernel and user-space code run against real RTL.

Host-speed processor model

A generic processor executing C/C++ at host speed while generating cycle-accurate bus traffic into the RTL. Develop the test suite fast, then validate it in full RTL simulation.

Functional platforms

A functional model that implements the real register map and stands in for a whole subsystem, so firmware development starts months before that RTL exists.

Proven on a LiDAR ASIC test suite, an AR SoC's Tensilica accelerator interfaces, and the DMA subsystem of a visual tracking accelerator. Case study →