Baremetal ARM: CoreSight & SMMUv3
Almost every public reference for CoreSight and SMMUv3 assumes a Linux kernel driver is doing the work. Pre-silicon emulation, first power-on and real-time firmware do not have one. We bring these subsystems up without it.
CoreSight
- ETM trace-source configuration, funnel routing, ETB and ETR sink setup, programmatic trace capture from baremetal code.
- Topology walks that prove every component is connected and operational, run on Veloce and Palladium before RTL freeze.
- Cross Trigger Interface, Embedded Logic Analyzer and System Trace Macrocell coverage for CoreSight 600.
- Debug and trace attachment for DSP cores on FPGA over both JTAG and CoreSight, with Lauterbach and vendor tooling.
SMMUv3
- Stream-table configuration, stage 1 and stage 2 translation setup, fault handling.
- Wiring a custom accelerator through the SMMU with no kernel driver, and diagnosing caching, DMA and system-MMU interactions in complex memory subsystems.
- Linux IOVA allocation and IOMMU sharing between user-space and DMA hardware when a kernel is present.
Also
- Multi-core job scheduling frameworks that run transparently on baremetal, Linux, XTOS and XOS.
- Hardware-mailbox communication protocols across distinct processor and DSP architectures.
- Pre- and post-silicon test frameworks that are the official validation sign-off environment.