Custom silicon IP,
from spec to running prototype.
We take a block, a subsystem or an accelerator from architecture specification through RTL and verification to a working prototype, and hand your SoC team integration-ready IP with software already executing on it.
Three stages. One team. No handoff gaps.
Most firms sell one stage. Architecture shops hand off a spec. RTL shops need one handed to them. Verification arrives after RTL, firmware waits for silicon. We have done every stage on the same engagement, on billion-transistor silicon.
Architect
A controlled specification the RTL team can build from and the software team can code against.
- Workload profiling and core selection
- Hardware and micro-architecture specs
- Bit-exact reference models
- PPA and memory-macro inventories
Implement
Verified, synthesizable IP with an integration guide and release tags.
- SystemVerilog RTL and HLS
- CDC-safe multi-clock design
- UVM, DPI and software-driven verification
- Integration benches across IP boundaries
Prototype
The design running, with software on it, before and after silicon.
- FPGA mapping and timing closure
- Palladium and Veloce emulation
- QEMU and virtual platforms
- Boards, firmware and bring-up
Proof at every stage
Architecting a five-stage visual tracking accelerator for a multi-camera XR SoC
Hardware architect of record for a fixed-function accelerator that turns four concurrent camera streams into a real-time 6DOF tracking match set, coordinating the client's RTL designers across fifteen IP repositories.
Making Tensilica DSPs a platform: integration guidelines, core wrapping and accelerator attachment for a multi-DSP AR SoC
A platform-wide integration guideline every Tensilica core on the SoC follows, a repeatable core-wrapping procedure with foundry memory macros, and an accelerator attachment model built on TIE queues and shared data RAM.
Where we go deeper than most
Tensilica DSP & TIE
Core configuration, memory integration, TIE-attached accelerators, XTOS/XOS firmware.
Baremetal ARM: CoreSight & SMMUv3
Trace, debug and address translation brought up with no kernel driver in the loop.
Co-Simulation Platforms
QEMU and host-speed processor models driving cycle-accurate RTL, so firmware starts before RTL is done.
Spec-Driven RTL Delivery
Controlled specs, change notes, decision registries and integration benches for distributed RTL teams.
Camera & Sensor Pipelines
MIPI, GMSL2, GigE Vision, HDMI and event cameras, from PHY to frame buffer.
Vision, XR, DSP and defense prototypes
AR and XR headset silicon. Edge vision and event cameras. Tensilica and ARM heterogeneous SoCs. LiDAR control ASICs. Assistive-vision wearables for NIH-funded research. FPGA pipelines for defense programs.
Small by design, senior by default
A PhD hardware architect, a hardware engineer from MIT Lincoln Laboratory, a kernel-level embedded software engineer, and specialist associates brought in for the engagements that need them. Meet the team →
Tell us what you need built.
Every engagement starts with a short, fixed-price statement of work with written acceptance criteria. If it goes well, the next one is easy.
Contact us