Notes from the bench
Practitioner writing on the topics where public material is thin: TIE, baremetal CoreSight and SMMUv3, Tensilica on FPGA fabric, and running distributed RTL teams against controlled specs.
Integrating custom hardware accelerators with Tensilica DSPs
How TIE queues, lookups and shared data RAM give Tensilica the most flexible accelerator attachment model we have evaluated, and what a hybrid RTL/transactional verification flow looks like in practice.
Baremetal CoreSight trace bring-up without a kernel
ETM configuration, funnel routing, ETB and ETR sinks, and programmatic trace capture on ARM systems where Linux is not in the loop.
FPGA in production: what the reference designs do not tell you
Versal-specific lane rules for MIPI, transceiver debug, and closing timing on multi-clock camera pipelines.
TIE instruction development from first principles
A practitioner walk-through of custom Tensilica instructions, state registers and queues, with measured cycle counts against the baseline.