Tensilica DSP & TIE
Tensilica cores are popular for a reason: software-centric high-performance compute, catalogued base configurations, and an extensible ISA. What gets lost is how flexible the accelerator attachment model is. We have spent seven years on that boundary.
What we do
- System design. Architectural exploration, core and feature selection, virtual prototyping. Profiling and synthesizing configurations across ISA extensions, SIMD widths, DMA options, cache hierarchy and custom external interfaces.
- DSP integration. Core configuration through XPG, memory integration with foundry macros, subsystem integration, platform-wide integration guidelines, CoreSight debug attachment, and pre-silicon verification.
- Accelerator attachment. Compute accelerators coupled through TIE input and output queues, lookups and shared data RAM, verified with a hybrid RTL and transactional flow bridged over SystemVerilog DPI.
- Embedded software. XTOS and XOS, multi-core heterogeneous DSP development, hardware mailboxes and DMA drivers, advanced debug.
- ISA customization. TIE instruction, state and queue development, with the toolchain running in-house.
Why us
- Cadence Tensilica partner under a Cadence license agreement.
- Speaker at Cadence LIVE 2025 on integrating custom accelerators with Tensilica DSPs.
- Two people on the team with production TIE and Xtensa platform experience, plus the architect who wrote the integration standard for a multi-DSP SoC.
- Demonstration of a TIE-attached accelerator on FPGA planned for Embedded Vision Summit 2026.
Case study: making Tensilica DSPs a platform →
Case study: Q8 DSP and TIE queue verification for a LiDAR ASIC →