Three custom IP blocks for a low-power AR SoC: hardware logging, mailbox synchronization and event generation
Architectural specifications for three infrastructure IP blocks, RTL and verification for two of them, oversight of the third, and integration guidance to the chip team.
The challenge
A multi-core SoC with several DSP architectures needed infrastructure blocks that the application teams could not live without: a way to log and trace from every core without stealing DSP cycles, a way for cores to synchronize and signal each other, and a way to trigger events between subsystems. Each block spanned multiple clock domains.
What we owned
Hardware logging accelerator. Cores inject messages into a hardware queue. The block timestamps, packetizes, optionally compresses and encrypts, buffers, and signals system DMA to drain to an on-chip or off-chip endpoint. Messages carry a source ID and a channel; channels can be locally or globally associated, rate limited, and configured to block, drop or wrap on overflow. Binary, tokenized and plain-text logs are supported, along with software-instrumented tracing: when any core detects a critical condition it suspends a global channel, which snapshots the trace history of every core around the event. APB control, ATB trace egress.
Mailbox and synchronization block. Thirty-two mailboxes with set, clear, status and mask registers and combinational interrupt generation, behind a multi-window APB decoder spanning three clock domains. Atomic operations for multi-core synchronization.
Event-generation block. A companion block for triggering between subsystems, verified alongside the mailbox in a hardware/software co-simulation framework ported to Synopsys VCS.
Specification and integration. Architectural specifications for all three. RTL and verification for two, with CDC mitigation designed in; oversight of the third. Detailed documentation and guidance to the integration team on instancing and interconnecting the blocks in the full-chip design.
Outcome
Three infrastructure blocks in the chip, with a logging path that costs the DSPs almost nothing and a debug capability the software teams use every day.