A production multi-client AXI-Stream DMA engine inside a dual-camera capture bridge
A parameterized native DMA engine with its own micro-architecture specification, shipped inside a multi-clock dual-camera capture bridge with full timing closure on a 7-series FPGA.
The challenge
Two camera streams had to be captured concurrently into off-chip memory while a host debug port read and wrote the same memory, all across independent clock domains, on a cost-constrained 7-series device. The design had to be production quality: documented, verified, timing-closed.
What we owned
Architecture and RTL. A dual-camera interface bridge with a custom multi-clock memory arbiter handling two camera ingress streams plus host ingress and egress. At its core, a parameterized native DMA engine with AXI-Stream client interfaces on both write and read sides, multi-client request moderation and context management, a native command/request/data bus toward the memory completer, and configuration and error-syndrome reporting. Protocol adaptation to AXI is layered above it, so the engine is reusable.
Specification. A Micro-Architecture Specification for the DMA engine covering the request moderator, control block and the write and read transfer managers, so the client can maintain and extend it.
Verification. A memory simulation model derived from the component datasheet timing, and a full RTL verification run in Questa with SystemVerilog DPI emulating the host interface.
Physical implementation. Vivado implementation with full timing closure across all clock domains.
Outcome
A shipped, documented, reusable DMA engine and a capture bridge that met its throughput and timing targets on the first production build.