A Versal FPGA prototyping platform for a perception SoC: software architecture, Linux and real-time bring-up, MIPI display path and multicore DSP debug

The challenge

The client’s VLSI team needed an FPGA platform to prototype a perception SoC: application and real-time processors, a display subsystem, custom IP in the fabric, and DSP cores that engineers could debug. They needed it to serve the immediate demo and the prototypes after it.

What we owned

System architecture specification. A written software architecture for the Versal MPSoC platform covering application processors, real-time processors, display subsystem and custom IP subsystems, designed for the short-term demonstration while remaining extensible.

Processing-subsystem bring-up. A custom embedded Linux image for the application cluster, a real-time runtime for the RTPs, inter-processor communication and tasking, and drivers for client-provided IP.

MIPI display path. An FPGA design around the AMD MIPI CSI-RX and DSI-TX IP with a camera-to-display loopback through DDR frame buffers. FMC adaptor selection with pinout and voltage review before procurement, then rework of pin placement to AMD’s Versal lane rules and a full implementation run to de-risk the client’s custom FMC before it existed. Demonstrated on an LCD panel; Vivado and Vitis projects delivered as reference.

Multicore DSP debug. Debug of client DSP cores on FPGA over both direct JTAG and ARM CoreSight, validated on-chip. A costed comparison of a single-vendor Lauterbach solution against Vitis plus Xplorer, covering cross-trigger halting across cores and both off-chip and on-chip instruction trace. A bridge from the Xtensa on-chip debug protocol to the AMD hardware server. Transceiver-level HDMI debug in collaboration with AMD support.

Outcome

All tasks completed against written acceptance criteria and closed with a signed completion report. The platform is now the client’s prototyping baseline.