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Work / Pre-silicon verification

CoreSight verification on Veloce, with a clock-domain-crossing defect caught before RTL freeze

Baremetal tests across ARM-A and ARM-M cores proving every CoreSight component connected and operational for a mission-mode crash-dump facility, run on Siemens Veloce ahead of tape-out.

ClientARMv9 multicore SoC vendor
Period2024 to 2026
Stages
  • Prototype
Tools
  • Siemens Veloce
  • ARM CoreSight 600
  • CTI
  • ELA-600
  • STM-500
  • Baremetal C
  • Waveform debug

The challenge

A complex ARMv9 SoC depended on its CoreSight debug and trace infrastructure for a mission-mode crash-dump facility. If any component was mis-connected, the feature would fail in the field. The infrastructure had to be proven on emulation before RTL freeze, without Linux in the loop.

What we owned

Test development. Baremetal code for both ARM-A and ARM-M profile processors that walks the CoreSight topology, exercises each component, and verifies integration and function. Tests were executed on Veloce with waveforms captured for every failure.

Debug. Several connectivity and configuration defects in the customer’s CoreSight implementation were isolated from those waveforms. The most consequential was a missing clock-domain-crossing component between the processor and debug subsystems, an RTL bug that would have shipped.

Coverage growth. We managed a test developer extending the framework to cover CoreSight 600 components including the Cross Trigger Interface, Embedded Logic Analyzer and System Trace Macrocell before freeze.

Outcome

A verified debug fabric, a critical CDC defect fixed in RTL rather than in silicon, and a reusable baremetal CoreSight test framework. The same approach underpins our baremetal CoreSight specialty.

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